Factors Impacting Wafer-Level Test Productivity

Factors Impacting Wafer Level Test ProductivityIn general, analytical probers used in test labs or fabless facilities are not equipped with automatic Probe-to-Pad Alignment (PTPA) technologies. PTPA errors must be corrected manually, adding unnecessary delay to obtain the desired wafer-level test data and limit test productivity. Due to PTPA errors induced by thermal drift during unattended testing over multiple temperatures, wafer probers are unable to make measurements and collect data during idle time and alignment correction time, negatively impacting on the overall wafer-level test productivity. These two areas are examined more closely here:

Idle time
Without a capability to automatically correct PTPA errors caused by thermal drift, it is impossible to run a wafer prober over multiple temperature set-points without an operator. Either an operator must manually correct PTPA errors after each temperature change, or a wafer prober will be idle until the correction is made. Tasking operators to come in after hours to make the corrections, or running multiple shifts, or reducing the number of temperatures for a protocol could have an adverse impact on the cost of test, or could compromise the data gathered. For test plans that span several days, it is very possible that idle time constitutes a 25-50% productivity loss for the wafer prober and the complete test cell instrumentation.

Alignment correction time
Without automatic PTPA correction, alignment errors must be manually adjusted between temperature changes, which can be very time consuming when wafer probe arrays are large or pad sizes are very small. This is particularly true for positioner-based probes. When automatic PTPA is employed, the corrections are inherently fast. Overall, this is the smallest wafer test time segment to cause productivity loss.

New on-site PTPA correction such as VueTrack technology utilizes a single downward-looking microscope to measure the probe tips and wafer locations with the chuck in the same position that the electrical measurement (or probe contact) will be made. Furthermore Cascade Microtech provides high thermal stability (HTS) enhancements – components made of high thermally stable materials – to minimize thermal drift. On-site probe tip and wafer location measurements in combination with HTS enhancements enable the best possible alignment to be maintained throughout a wafer-level test plan, and eliminate these drains on wafer-level test productivity.

If you use VueTrack, we’d love to see what productivity gains you’ve realized. If you’ve actually measured before and after wafer-level test results, leave a comment in the comment field below. 

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